1. Field of the Invention
The present invention relates to a CDMA (Code Division Multiple Access) receiving apparatus which receives and demodulates a direct sequence CDMA signal produced through QPSK (Quadrature Phase Shift Keying) spreading modulation.
In the DS-CDMA (Direct Sequence CDMA) method, as a modulating method, the BPSK (Binary Phase Shift Keying) method, or the QPSK method is selected. When the QPSK method is used, an in-phase signal and a quadrature signal undergo spreading modulation using different spreading codes, and are combined in a transmitting apparatus. The thus-produced signal is transmitted from the transmitting apparatus. A CDMA receiving apparatus demodulates the received signal into the in-phase signal and the quadrature signal, and despreading processing is performed on the in-phase signal and the quadrature signal using despreading codes which are caused to be in synchronization with the spreading codes, respectively. Reduction of the cost of such a CDMA receiving apparatus is demanded.
2. Descriptions of the Relate Art
FIG. 1 illustrates a CDMA receiving apparatus in the related art, and shows part of the CDMA receiving apparatus which uses the above-mentioned QPSK spreading modulation. As shown in FIG. 1, the CDMA receiving apparatus includes an antenna 51, a high-frequency amplifier 52, a bandpass filter 53, demodulators 54, 55, a carrier wave generator 56, a phase shifter (xcfx80/2) 57 for shifting the phase of a signal input thereto by xcfx80/2, A-D converters (A-D) 58 and 59, despreading portions 60, 61, 62 and 63, adders 64, 65, a fading compensating portion 66 and a determining and outputting portion 67.
The direct sequence CDMA signal, transmitted from a transmitting apparatus, obtained through the QPSK spreading modulation is input to the CDMA receiving apparatus through the antenna 51. The high-frequency amplifier 52 amplifies the thus-input signal. The bandpass filter 53 removes unnecessary frequency band components from the amplified signal. The carrier wave from the carrier wave generating portion 56 is input to the demodulator 54 directly and to the demodulator 55 via the phase shifter 57 which shifts the phase of the carrier wave by xcfx80/2, and, thus, coherent detection is performed through the demodulators 54 and 55 on the signal output from the bandpass filter 53. The thus-obtained signals are a demodulated in-phase signal and a demodulated quadrature signal, and are converted into digital signals through the A-D converters 58, 59, respectively. Then, the thus-obtained signals are input to the despreading portions 60, 61, 62 and 63. The despreading codes Ci, Cq, which are in synchronization with the spreading codes used in the transmitting apparatus as mentioned above, are input to the despreading portions 60, 61, 62 and 63. Thus, despreading processing is performed on the signals output from the A-D converters 58 and 59. The thus-obtained signals are added as shown in FIG. 1 through the adders 64 and 65. Thus, the in-phase signal and the quadrature signal are obtained. The in-phase signal and the quadrature signal are then input to the fading compensating portion 66 and the fluctuations of the signals occurring due to the fading in the propagation path are compensated. Then, determination processing is performed on the thus-obtained signals through the determining and outputting portion 67. Then, the received signal is output from the determining and outputting portion 67.
FIG. 2 illustrates a spreading QPSK modulating portion, and shows an arrangement of a portion for performing digital processing so as to obtain the direct sequence CDMA signal through QPSK modulation. Di and Dq represent an in-phase transmission information symbol and a quadrature transmission information symbol, respectively. Ci and Cq represent a spreading code for the in-phase signal and a spreading code for the quadrature signal, respectively. Si and Sq represent the in-phase signal and the quadrature signal obtained through spreading modulation, respectively. The in-phase transmission information symbol Di, the quadrature transmission information symbol Dq, and the spreading codes Ci and Cq for the in-phase signal and for the quadrature signal are input to exclusive OR circuits 71, 72, 73 and 74. Then, through level converting portions 75, 76, 77 and 78, for example, xe2x80x9c0xe2x80x9d is converted into xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d is converted into xe2x80x9cxe2x88x921xe2x80x9d. Then, the thus-obtained signals are added through adders 79 and 80. Then, the in-phase signal Si and the quadrature signal Sq are output. The transmitting apparatus forms a QPSK-modulated signal from the in-phase signal Si and the quadrature signal Sq, and transmits the QPSK-modulated signal.
FIG. 3 illustrates a general arrangement of a matched filter. Such a matched filter can be applied to a portion for the synchronization of the despreading codes and to each of the despreading portions 60, 61, 62 and 63 shown in FIG. l. The arrangement of FIG. 3 includes one-chip-time delaying elements (D) 81-1 through 81-n, multipliers 82-0 through 82-n, and an adder 83. To this arrangement, a signal S is input. Further, to the multipliers 82-0 through 82-n, the despreading codes C0 through Cn are input, respectively.
When the matched filter comprising the above-described arrangement is applied to each of the despreading portions as mentioned above, the delaying elements 81-1 through 81-n form shift registers for shifting the input signal S every one chip time. The input signal S, the output signals of the shift registers and the despreading codes C0 through Cn are input to the multipliers 82-0 through 82-n, respectively, as shown in FIG. 3. The signals output from the multipliers 82-0 through 82-n are added through the adder 83. The output signal of the adder 83 is a despread and demodulated output signal for one symbol.
FIG. 4 shows a general arrangement of a sliding correlator. The sliding correlator can be applied to each of the despreading portions 60, 61, 62 and 63 shown in FIG. 1. The arrangement shown in FIG. 4 includes a multiplier 91, an adder 92, a one-chip-time delaying element (D) 93, and a switch 94 which is closed by a control signal SB, the period of which is the symbol period.
When the sliding correlator is applied to each of the despreading portions as mentioned above, the input signal S and the despreading code C are input to the multiplier 91 which performs multiplication thereof. The multiplication output signal output from the multiplier 91 and the addition output signal output from the adder 92, which has been delayed by the time for one chip through the delaying element 93, are input to the adder 92 which performs addition thereof. Thus, integration is performed during the period for one symbol. When the switch 94 is closed by the control signal SB, the despread demodulated output signal for one symbol can be obtained.
When the QPSK modulation method is applied to the direct sequence CDMA method, the spreading QPSK modulating portion in the transmitting apparatus can be embodied by, for example, using the arrangement shown in FIG. 2. In this case, by treating the operation (Di+jDq).(Ci+jCq) performed by the exclusive OR circuits 71, 72, 73 and 74 shown in FIG. 2 as multiplication of the complex spreading series, despreading can be performed by complex multiplication using the complex conjugate values of the complex despreading code series. However, when despreading is performed by the complex multiplication, because a multiplier is needed, the circuit scale is large, and/or, an amount of data processing for performing the calculation is large.
An object of the present invention is to reduce the circuit scale of the despreading portions or to reduce the amount of calculation performed by the despreading portions.
A CDMA receiving apparatus according to the present invention receives a direct sequence CDMA signal produced through QPSK spreading modulation, performs coherent detection of the direct sequence CDMA signal, and despreads the signals, obtained through the coherent detection, through a despreading portion 10. The despreading portion 10 comprises a selector portion 13. The selector portion 13 selects signals as a demodulated and despread in-phase output signal and a demodulated and despread quadrature output signal, in accordance with despreading codes, from demodulated in-phase and quadrature signals obtained through the coherent detection, and inverted in-phase and quadrature signals obtained as a result of the signs of the demodulated in-phase and quadrature signals being inverted.
The despreading portion may include:
an in-phase shift register for shifting the demodulated in-phase signal every chip period;
a quadrature shift register for shifting the demodulated quadrature signal every chip period;
selector means, each element thereof for having signals, output from a respective element of the in-phase shift register and a respective element of the quadrature shift register, and signals, obtained as a result of the signs of the signals output from the respective element of the in-phase shift register and the respective element of the quadrature shift register being inverted, input thereto, selecting signals, as a selected in-phase signal and a selected quadrature signal, therefrom, and outputting the thus-selected signals;
in-phase adding means for adding the selected in-phase signals and outputting the addition result as the demodulated and despread in-phase output signal; and
quadrature adding means for adding the selected quadrature signals and outputting the addition result as the demodulated and despread quadrature output signal. Thus, the despreading portion can be formed by applying a matched-filter-type arrangement thereto.
The despreading portion may include:
selector means for having the demodulated in-phase signal and the demodulated quadrature signal, and an inverted in-phase signal and an inverted quadrature signal, obtained as a result of the signs of the demodulated in-phase signal and the demodulated quadrature signal being inverted, input thereto, selecting signals therefrom, as a selected in-phase signal and a selected quadrature signal, in accordance with the despreading codes, and outputting the thus-selected signals; and
adding means for adding the selected in-phase signal and adding the selected quadrature signal during the period for one bit, and outputting the addition results as the demodulated and despread in-phase output signal and the demodulated and despread quadrature output signal. Thus, the despreading portion can be formed by applying a sliding-correlator-type arrangement thereto.
Other objects and further features of the present invention will become more apparent from the following detailed descriptions when read in conjunction with the accompanying drawings.